Electronic device with data storage device

ABSTRACT

An electronic device ( 100 ) has a data storage device ( 120 ) for storing N data elements, the data storage device ( 120 ) comprising a first collection ( 122 ) of data storage elements ( 130 ). The first collection ( 122 ) of data storage elements ( 130 ) is accessible through an address decoder ( 140 ). In a shift register mode of the data storage device ( 120 ), the address decoder ( 140 ) is responsive to an address generator ( 160 ) comprising a modulo-N counter. Rather than having to shift data elements from one data storage element ( 130 ) to another, the address generator ( 160 ) generates a pointer to the data storage element ( 130 ) that contains the data element that is to be shifted out of the shift register. This has the advantage that the output of a predecessor data storage element ( 130 ) in a shift register need not be interconnected to the input of its successor. In addition, the amount of data traffic required during a shift is drastically reduced. The invention is particularly relevant to reconfigurable logic devices that use look-up tables for implementing shift registers.

The present invention relates to an electronic device comprising a datastorage device for storing N data elements, N being an integer with avalue of at least two, the data storage device comprising a firstcollection of data storage elements, and an address decoder having anoutput coupled to the first collection of data storage elements foraccessing a data storage element from the first collection of datastorage elements on the basis of a bit pattern.

Nowadays, virtually all electronic devices, e.g., integrated circuits(ICs), systems-on-chip (SoCs) and so on, include a data storage devicecoupled to an address decoder for storing and retrieving data from aparticular data storage element of the data storage device based on abit pattern, i.e., an address. Such a data storage device may be adedicated storage device, e.g., a volatile or non-volatile memory, or areconfigurable logic device (RLD), e.g. an field-programmable gate array(FPGA), which can be configured to operate as data storage device in adata storage mode of the RLD. An application of such a data storagedevice may be a shift register implementation, which implies that thedata stored in the data storage device is retrieved from the datastorage device a fixed number of clock cycles later.

RLDs from the Virtex-II family by Xilinx, as described in the Virtex-IIPlatform FPGA handbook, Xilinx, 2000, includes a look-up table (LUT)that is operable as a shift register. To this end, the data storageelements of the LUT are implemented by means of interconnected latches,which are arranged to ripple data from latch to latch under control of acontrol signal. This way, the LUT operates in a pipeline-like fashionwith the data element being shifted into the first data storage elementand being retrieved from the last data storage element in the pipelineafter it has been shifted through the complete pipeline.

It is a disadvantage that for shift register implementations of datastorage devices like the LUT in the RLD from Xilinx the data storageelements have to be interconnected to implement the shift registerbehavior of the device because this interconnection introducesadditional wiring, i.e., interconnects, between the various data storageelements of the first collection of data storage elements, as well asadditional transistors for disconnecting the interconnections if theelectronic device is operated in a non-shift register configuration.

Amongst others, it is an object of the invention to provide anelectronic device of the opening paragraph that allows for a moreefficient implementation of the first collection of data storageelements for shift-register implementations.

Now, the object of the invention is realized by an input of the addressdecoder being coupled to an address generator comprising a modulo-Ncounter for generating the bit pattern. This has the advantage that itis no longer necessary to physically shift data from a data storageelement to the next data storage element in the data storage device.Therefore, the interconnections between the various data storageelements that enable this shifting of data can be omitted. Instead, theaddress generator generates addresses from an address space thatrepresents the temporal behavior of a shift register. In other words,rather than physically moving data elements from one data storageelement to another, a reference, e.g., an address, of the data elementthat has to be retrieved from the data storage device is generated onthe fly. This has the additional advantage that only a single datastorage element has to be overwritten, i.e., the data storage elementfrom which the data element is retrieved, rather than having tooverwrite all N data storage elements in the known implementations ofshift registers.

Advantageously, the electronic device comprises a look-up table beingoperable as the first collection of data storage elements in a datastorage configuration of the electronic device.

The present invention is especially useful for application in RLDs basedon LUTs, because in such devices both the amount of hardware requiredand the performance of the device are bottlenecks in the design and useof the devices. Thus, the reduced amount of required interconnect andthe reduced amount of data communication of shift registerimplementations of the present invention contribute to an increase inperformance and a reduction in design effort for such RLDs. Moreimportantly, the area overhead of the RLD is reduced, because noadditional switches, e.g., transistors, are needed to disconnect thedata paths between the data storage elements if the RLD is operated in anon-shift register configuration.

It is an advantage if the electronic device is arranged to perform aread operation on the data storage element in a first part of a clockcycle; and to perform a write operation on the data storage element in asecond part of the clock cycle.

This functionality, which may be implemented as a Random Access Memory(RAM) type architecture of the data storage device, prevents read/writeconflicts during a single clock cycle, which implies that a singleaddress decoder can be used for both reading and writing from and to adata storage element, which is a substantial advantage in terms of area,especially in the field of RLDs, where usually separate decoders arebeing used for writing and reading. The functionality may be implementedby a configurable switch that couples the data input of the data storagedevice to a memory element of the data storage element; the configurableswitch being conductive during at least a part of the second part of theclock cycle. Only if this switch is conductive, i.e. during the writecycle, can data be stored in the data storage element.

It is a further advantage if the data storage device further comprisinga second collection of data storage elements at least during a datastorage mode of the electronic device; the electronic device furthercomprising control circuitry coupled between the control signal and thedata storage device for selecting one of the first and secondcollections of data storage elements responsive to a selection signal.

Such an arrangement allows for shift register implementations that havea larger size than the size of a single collection of data storageelements, e.g., a LUT, with the control circuitry controlling theselection of the appropriate collection of data elements. The secondcollection of data storage elements may be responsive to a differentaddress decoder or to the address decoder of the first collection ofdata storage elements, e.g., as is the case for multiple-output LUTs.The collections of data storage elements need not be permanentlyintegrated in the data storage device; for instance, if the electronicdevice is a reconfigurable device, the second collection of data storageelements may be added to the data storage device in a data storageconfiguration, e.g., a memory configuration or a shift registerconfiguration, of the electronic device

It is yet a further advantage if the data storage device comprises athird collection of data storage elements and a fourth collection ofdata storage elements being at least in the data storage configurationof the electronic device, the third collection and the fourth collectionof data storage elements being responsive to a further address decoder;the control circuitry further being arranged to select one of the first,second, third and fourth second data storage elements responsive to theselection signal and a further selection signal. The inclusion of alarger number of collections of data storage elements, e.g., LUTs, undercontrol of the control circuitry allows for the construction of a largesize shift registers, which can be particularly useful for applicationsthat require large shift registers for the buffering or delaying ofdata, e.g., digital signals processors (DSPs). Such an architecture maybe configured by the most significant bits from the bit pattern.

It is a further advantage if the control circuitry further comprises aconfiguration network for configuring a size of the data storage device.The inclusion of such a network enables the dynamic selection of thenumber of the collections of data storage elements that are temporarilyincluded in the data storage device, for instance during itsimplementation as a shift register.

The electronic device and parts thereof according to the invention aredescribed in more detail and by way of non-limiting examples withreference to the accompanying drawings, wherein:

FIG. 1 depicts an embodiment of an electronic device of the presentinvention;

FIG. 2 depicts an exemplary data storage element;

FIG. 3 depicts another embodiment of an electronic device of the presentinvention;

FIG. 4 depicts yet another embodiment of an electronic device of thepresent invention;

FIG. 5 depicts a further embodiment of an electronic device of thepresent invention;

FIG. 6 a depicts an embodiment of a control circuit of the presentinvention; and

FIG. 6 b depicts an embodiment of a data routing network of the presentinvention.

In FIG. 1, electronic device 100 includes a data storage device 120 forstoring N data elements 130, N being an integer with a value of at leasttwo; in FIG. 1, N is sixteen, this particular number being chosen forreasons of mere example only. The data storage device 120 has a firstcollection 122 of data storage elements 130. The first collection 122 ofdata storage elements 130 is coupled to a control input 126 and a datainput 124. The first collection 122 of data storage elements 130 may bea dedicated data storage device, e.g. a volatile or non-volatile memory,or a look-up table (LUT), in which case the electronic device 100 may bea RLD. In FIG. 1, the first collection 122 of data storage elements 130combined with address decoder 140 would form a 4-input LUT.

The electronic device 100 also includes an address decoder 140 having anoutput 142 coupled to the first collection 122 of data storage elements130 for accessing a data storage element 130 from the first collection122 of data storage elements 130 on the basis of a bit pattern, e.g., anaddress of the data storage element 130 provided through a plurality ofoutputs 142. Each data storage element 130 is coupled to an output 142,which serves as a select line for the data storage element 130. An inputof the address decoder 140 is coupled to an address generator 160comprising a modulo N counter for generating the bit pattern responsiveto control signal 126 or another control signal being synchronized withcontrol signal 126. Control signal 126 may be a clock signal, with theaddress generator 160 being responsive to one of the edges of the clocksignal. The modulo N counter may be implemented in a separate datastorage device, e.g. a separate LUT.

This arrangement is particularly suitable for implementing shiftregister functionality in the data storage device 120. The modulo Ncounter of address generator 160 ensures that at each occurrence of acontrol signal, i.e., control signal 126 or its synchronizedcounterpart, a next data storage element 130 is selected in data storagedevice 120. This way, all N data storage elements 130 are selected onceduring N control cycles, preferably in a cyclic way. Basically, theaddress generator 160 generates a pointer to a data storage element 130,that pointer being pointed once to each of the N data storage elements130, thereby implementing an N-stage shift register without having toactually shift data elements from one data storage element 130 toanother. Therefore, the data storage elements 130 no longer need aninterconnected data path, i.e., a data output from the predecessor datastorage element 130 being connected to a data input of its successor inthe shift register, because the data is no longer physically rippledthrough the shift register. This has the additional advantage of reduceddata communication and increased data integrity, because the physicalrippling of data through a shift register means that for each datastorage element 130 care has to be taken that a read action takes placebefore a write action. The implementation of the present inventionreduces this problem to a single data storage element 130, i.e., theelement being selected by address generator 160.

In addition, it is emphasized that the modulo N counter may beprogrammable, i.e., that N may be dynamically defined. This allows forimplementations where the actual size of the shift register is smallerthan the total capacity of a data storage device 120.

In case of a multi-functional implementation of the first collection 122of data storage elements 130, e.g., a LUT implementation within a RLD,the coupling between the address decoder 140 and the address generator160 may be configurable, in order to disconnect or bypass the addressgenerator 160 in order to access the inputs of address decoder 140, forinstance during a memory mode or a combinatorial mode of the firstcollection 122 of data storage elements 130. Alternatively, the addressgenerator 160 may become transparent in the absence of a control signal126 or its synchronized counterpart.

Now, the remaining FIGS. will be described in backreference to FIG. 1.Corresponding reference numerals will have similar meanings unlessexplicitly stated otherwise. In FIG. 2, an example implementation of adata storage element 130 is shown. Data storage element 130 has a memoryelement formed by interconnected inverters 133 and 134. The input of thememory element is interconnected to a portion of the data input 124 ofthe first collection 122 of data storage elements 130. This portionincludes a first enable switch 131 and a second enable switch 132. Firstenable switch 131 is controlled by a select signal via output 142 fromthe address decoder 140. Second enable switch 132 is controlled bycontrol signal 126, which may be a clock signal, an inverted clocksignal or another multi-phase signal. The memory element has an outputincluding third enable switch 137 being controlled by the select signalfrom output 142. All switches are preferably implemented as transistors,as shown in FIG. 2, although other implementations are feasible.

During a first phase of the control signal 126, second enable switch 132is disabled and updating of the memory element formed by inverters 133and 134 is prohibited, even if the data storage element 130 is selectedby address decoder 140, i.e., first and third enable switches 131 and137 are enabled via output 142. This mechanism ensures that during afirst phase of the control signal 126 data stored in the memory elementcannot be overwritten. Hence, the first phase of the control signal 126is used to read out data element from data storage element 130. In thesecond phase of control signal 126, second enable switch 132 is enabledand the memory element can be updated.

It is emphasized that the implementation of data storage element 130shown in FIG. 2 is shown by way of a non-limiting example only. Otherequivalent implementations of the data storage element 130 are equallyfeasible without departing from the scope of the present invention.

The present invention may also be applied to data storage devices thatare capable of storing N data elements in K collections of data storageelements, each collection having a capacity of M data storage elements;i.e., N=K*M, with K and M both being integers with a value of at leasttwo. This way, larger shift registers comprising several collections ofdata storage elements may be built. FIG. 3 shows an implementation of anelectronic device 100 that is capable of implementing a shift registerin such a way.

The data storage device 120 of electronic device 100 has a firstcollection 122 and a second collection 222 of data storage elements 130,both collections 122 and 222 being accessible by address decoder 140.Data storage device 120 may be a dedicated multi-column memory device ora multi-column, multi-purpose device, e.g. a multiple-output LUT. Theselection of the appropriate data storage element 130 from theappropriate collection, i.e., first collection 122 or second collection222, is controlled by control circuitry 180 implementing demultiplexerfunctionality, which is symbolically depicted by demultiplexer 210,which has an input coupled to control signal 126 and outputs coupled tothe first collection 122 and the second collection 222 of data storageelements 130. The demultiplexer 210, or the equivalent controlcircuitry, is responsive to a selection signal 165, e.g., the mostsignificant bit from the outputs of the address generator 160. It willbe obvious that a similar control architecture may be used todemultiplex a global data input 124 not shown to the first collection122 and second collection 222. Alternatively, if each of the firstcollection 122 or second collection 222 of data storage elements 130 hasa separate data input, a collection of multiplexers may be used to routethe input to the appropriate collection of data storage elements, inanalogy with the teachings of FIG. 6 a and FIG. 6 b. It may beadvantageous to add a multiplexer 250 to the data outputs of the firstcollection 122 and second collection 222 of data storage elements 130,in order to convert a multiple-output data storage device into a singleoutput data storage device during the implementation of the shiftregister functionality. Multiplexer 250 may be controlled by selectionsignal 165, e.g., the most significant bit. The first collection 122 ofdata storage elements 130 may have a bypass path 251 around multiplexer250 and the second collection 222 of data storage elements 130 may havea bypass path 252 around multiplexer 250 for operating the data storagedevice 120 in a multiple-output mode when another functionality, e.g.,implementation of a logic function in a combinatorial mode of a LUT,than the shift register implementation is required. Obviously, one ofthe bypass paths may be omitted if the multiplexer 250 can be tied to afixed selection signal in this mode.

FIG. 4 is described in backreference to FIG. 3. Corresponding referencenumerals will have similar meanings unless explicitly stated otherwise.FIG. 4 shows an alternative implementation of the data storage device120 shown in FIG. 3. The first collection 122 of data storage elements130 is still accessible by address decoder around multiplexer 250. Thesecond collection 222 of data storage elements 130 is accessible by afurther address decoder 240. In the shift register implementation modeof data storage device 120, further address decoder 240 is coupled tothe address generator 160, or to another address generator that operatesin a lock-step mode, i.e., synchronized, with the address generator 160.Basically, the electronic device 100 in FIG. 4 joins independentcollections of data storage elements; e.g., independent LUTs fromseparate FPGA cells, into a single data storage device 120 forimplementing a shift register.

FIG. 5 is described in backreference to FIG. 4. Corresponding referencenumerals will have similar meanings unless explicitly stated otherwise.In FIG. 5, the concepts shown in FIG. 3 and FIG. 4 have been combined.Electronic device 100 includes a data storage device 120 that has afirst collection 122, a second collection 222, a third collection 322and a fourth collection 422 of data storage elements 130. The firstcollection 122 and the second collection 222 of data storage elements130 are accessible by address decoder 140, whereas the third collection322 and the fourth collection 422 of data storage elements 130 areaccessible by a further address decoder 240. Both address decoders 140and 240 are coupled to address generator 160, or a combination ofsynchronized address generators, in a shift register implementation modeof the data storage device 120. It is emphasized that data storagedevice 120 may comprise a first collection 122, a second collection 222,a third collection 322 and a fourth collection 422 of data storageelements 130 only during the shift register implementation mode, as aresult of the appropriate configuration of the control circuitry. Thiswill be explained in more detail later.

The control circuitry 180 now typically implements a single input/fouroutput demultiplexer functionality, which has been symbolically depictedby demultiplexers 210, 220 and 310. The demultiplexers may be controlledby a selection signal 165 and a further selection signal 164, e.g., thetwo most significant bits that are generated by the address generator160. Although shown for control signal 126, it will be appreciated thatsimilar control circuitry may be implemented for the various datasignals 124. On the output side of data storage device 120, additionalcontrol circuitry implementing the multiplexer functionally that issymbolically depicted by multiplexers 250, 260 and 320 may be used toconfigure the data storage device 120 into a single output mode duringits shift register implementation or another data storage mode ofelectronic device 100. Bypass paths 251, 252, 261 and 262 may be presentto allow a multiple output configuration of the first collection 122, asecond collection 222, a third collection 322 and a fourth collection422 of data storage elements 130.

FIG. 5 shows a combination of two two-output data storage devices, e.g.two two-output LUTs, into a single data storage device 120 forimplementing a shift register. It will be obvious to a person skilled inthe art that other combinations, e.g., several single-output datastorage devices, several multiple-output devices or a combination of thetwo, can be made without departing from the scope of the presentinvention.

FIG. 6 a shows an exemplary embodiment of a first part of controlcircuitry 180. In this particular example, a configuration network forthe data storage device 120 shown in FIG. 5 is given. The controlcircuitry 180 is responsive to configuration signals M1-M4, as well asto external selection signals S1 and S2 and internal selection signalsS3-S6. The selection signals S1 and S2 correspond with the selectionsignals 164 and 165 shown in FIG. 5. In this embodiment, controlcircuitry 180 has a twofold purpose; firstly, control circuitry 180 isarranged to configure an operational mode of the data storage device 120in response to configuration signals M1-M4, and secondly, controlcircuitry 180 is arranged to select the appropriate collection of datastorage elements 130, i.e., one of the first collection 122, a secondcollection 222, a third collection 322 and a fourth collection 422 ofdata storage elements 130, in response to selection signals S1-S6.

Multiplexers 602, 604, 608, 610, 612 and 614 are arranged to propagatethe control signal 126 to the appropriate collection of data storageelements in a memory mode, e.g., a shift register implementation, of thedata storage device 120. To this end, they have their input terminal 0,i.e., the input terminals that are selected when a logic ‘0’ is drivento the control terminal of the multiplexers, coupled to a signal path ofthis control signal. The input terminals 1, i.e., the input terminalsthat are selected when a logic ‘1’ is driven to the control terminals ofthe multiplexer, are coupled to a fixed logic value source providing alogic ‘0’, e.g., a pull-down transistor. The latter signal may beselected when the collections 122, 222, 322, 422 of data storageelements 130 are to be operated in a read-only mode, e.g., animplementation of a logic function in a combinatorial mode of a LUT.

Configuration bits M1 and M2, which configure the subdevices, e.g., thetwo-output LUTs, formed by the first collection 122 and secondcollection 222 of data storage elements 130, and by the third collection322 and fourth collection 422 of data storage elements 130 respectively,define whether or not these subdevices are to be operated in asynchronous mode, i.e., in a mode responsive to control signal 126. Inthis exemplary implementation, a value ‘1’ for M1 or M2 means that thecorresponding subdevice should be configured in a read-only mode. If oneof these configuration bits has a value ‘0’, the corresponding subdeviceis to be operated in a memory mode, and the data storage device 120 thenincludes one of the subdevices. If both configuration bits M1 and M2have value ‘0’, both are configured to be operated in a memory mode, anddata storage device 120 includes both subdevices 122/222 and 322/422.Selection bits S1 and S2 select the appropriate collection of datastorage elements 130. If both subdevices are included in data storagedevice 120, S1 and S2 represent the two most significant bits that aregenerated by the address generator 160. If only one of the subdevices isincluded in data storage device 120, S1 is set equal to S2.Alternatively, S2 can be tied to a fixed value, which may beprogrammable.

AND gate 620 has inputs coupled to M1 and M2. Its output is coupled toan input of OR gates 622 and 624, which have their other input connectedto S2 and the inverse, i.e., negation of S2 respectively. The latter hasbeen labeled S2!. The outputs of OR gates 622 and 624 are arranged toprovide selection signals S5 and S6 to the control terminals ofmultiplexers 602 and 604, respectively. This arrangement ensures that,if M1 and M2 are both a logic ‘1’ that both multiplexers 602 and 604will output the fixed logic ‘0’. In addition, it ensures that when atleast one of M1 and M2 is a logic ‘0’, only the subdevice thatcorresponds with the appropriate value of S2 is capable of receiving thecontrol signal 126. For instance, if M1=0, M2=0 and S2=1, selectionsignal S5 will be ‘1’ and selection signal S6 will be ‘0’.

Multiplexers 606 and 616 have their inputs connected to S1 and S2 undercontrol of configuration bits M3 and M4. These multiplexer can be usedto configure whether the subdevices are to operate as a single entity oras independent devices. In the former case, both multiplexers areconnected to S1, whereas in the latter case multiplexer 606 is connectedto S1 and multiplexer 616 is connected to S2 or vice versa. In thelatter case, it may be advantageous for the independent devices to beresponsive to independent control signals. The output signal and thenegation of the output signal of multiplexer 606 are provided to ORgates 626 and 628 respectively. The negation of the output signal isimplemented by inverter 642. OR gates 626 and 628 have their other inputconnected to M1. OR gate 626 provides selection signal S3 to the controlterminal of multiplexer 608, whereas OR gate 628 provides its outputsignal to the control terminal of multiplexer 610. Thus, if M1 has value‘1’, both collections 122, 222 of data storage elements 130 will be in aread-only mode, and if M1 has value ‘0’, the value of S1 or S2 willdecide which collection of data storage elements 130 is switched to amemory mode. It will be understood that OR gate 630, which generatesselection signal S4, and OR gate 632 implement an analogous controlmechanism for collections 322, 422 of data storage elements 130 viamultiplexers 612, 614 under the influence of inputs M2 and S1 or S2 andtheir negation implemented by inverter 644.

It will be obvious to those skilled in the art that many variations canbe made to the control circuitry shown in FIG. 6 a, which has been shownas a mere example only. Alternative implementations using differentcombinations of logic gates are equally acceptable. Less complex controlcircuitry may be used if the electronic device 100 does not require thelevel of flexibility provided by control circuitry 180. Alternatively,more complex control circuitry may be used if the electronic device 100requires more flexibility than the level of flexibility provided bycontrol circuitry 180. Also, it will be obvious to those skilled in theart that the control circuitry 180 of data storage devices of FIG. 3 andFIG. 4 can be easily derived from the control circuitry 180 shown inFIG. 6 a by removing redundant control elements.

FIG. 6 b shows an exemplary embodiment of the data path control part ofcontrol circuitry 180 for providing the appropriate data signals 124A-Dto the first collection 122, the second collection 222, the thirdcollection 322 and the fourth collection 422 of data storage elements130. The data path control part of control circuitry 180 is implementedby multiplexers 690, 692, 694 and 696 under control of the selectionsignals S3-S6 from FIG. 6 a. The data path control part of controlcircuitry 180 is arranged to select the number of appropriate number ofinputs to the subdevices 122/222 and 322/422, i.e., a single input ortwo independent inputs. For instance, if subdevice 122/222 requires twodifferent inputs, S3 and S5 will be set to the appropriate values toensure that the first collection 122 of data storage elements 130 iscoupled to either data input 124A or 124C, and the second collection 122of data storage elements 130 is coupled to data input 124B. Again, itwill be obvious to those skilled in the art that, dependent on therequired flexibility in the electronic device 100, the data path controlpart of control circuitry 180 can be amended accordingly withoutdeparting from the scope of the present invention.

It should be noted that the above-mentioned embodiments illustraterather than limit the invention, and that those skilled in the art willbe able to design many alternative embodiments without departing fromthe scope of the appended claims. In the claims, any reference signsplaced between parentheses shall not be construed as limiting the claim.The word “comprising” does not exclude the presence of elements or stepsother than those listed in a claim. The word “a” or “an” preceding anelement does not exclude the presence of a plurality of such elements.The invention can be implemented by means of hardware comprising severaldistinct elements. In the device claim enumerating several means,several of these means can be embodied by one and the same item ofhardware. The mere fact that certain measures are recited in mutuallydifferent dependent claims does not indicate that a combination of thesemeasures cannot be used to advantage.

1. An electronic device, comprising: a data storage device for storing Ndata elements, N being an integer with a value of at least two, the datastorage device comprising a first collection of data storage elements;and an address decoder having an output coupled to the first collectionof data storage elements for accessing a data storage element from thefirst collection of data storage elements on the basis of a bit pattern;characterized by further comprising an address generator comprising amodulo-N counter for generating the bit pattern.
 2. An electronicdevice, as claimed in claim 1, characterized by comprising a look-uptable being operable as the first collection of data storage elements ina data storage configuration of the electronic device.
 3. An electronicdevice as claimed in claim 1, characterized by being arranged to:perform a read operation on the data storage element in a first phase ofa control signal; and perform a write operation on the data storageelement in a second phase of the control signal.
 4. An electronic deviceas claimed in claim 3, characterized in that a data storage elementcomprises a configurable switch coupled between a memory element and adata input of the data storage device; the configurable switch beingconductive during at least a part of the second phase of the controlsignal.
 5. An electronic device as claimed in claim 3, characterized bythe data storage device further comprising a second collection of datastorage elements in at least a data storage configuration of theelectronic device; the electronic device further comprising controlcircuitry coupled between the control signal and the data storage devicefor selecting one of the first and second collection of data storageelements responsive to a selection signal.
 6. An electronic device asclaimed in claim 5, characterized by the second collection of datastorage elements being responsive to the address decoder.
 7. Anelectronic device as claimed in claim 5, characterized by the datastorage device comprising a third collection of data storage elementsand a fourth collection of data storage elements in at least the datastorage configuration of the electronic device, the third collection andthe fourth collection of data storage elements being responsive to afurther address decoder; the control circuitry further being arranged toselect one of the first, second, third and fourth collection of datastorage elements responsive to the selection signal and a furtherselection signal.
 8. An electronic device as claimed in claim 7,characterized in that the selection signal and the further selectionsignal are derived from the most significant bits of the bit pattern. 9.An electronic device as claimed in claim 5, characterized in that thecontrol circuitry further comprises a configuration network forconfiguring a size of the data storage device.